STC8A8K64D4 series

Features:

Core

• Enhanced 8051 Core with single clock per machine cycle (1T)

• Fully compatible instruction set with traditional 8051

• 43 interrupt sources and 4 interrupt priority levels

• Online debugging is supported

Operating voltage

• 1.9 to 5.5V

• Built-in LDO

Operating temperature

• -40°C~85°C

Flash memory

• Up to 64Kbytes of Flash memory to be used to store user code

• Configurable EEPROM size, 512bytes single page erased, can be repeatedly erased more than 100 thousand times.

• In-System-Programming, ISP in short, can be used to update the application code, no need for programmer.

• Online debugging with single chip is supported, and no emulator is needed. The number of breakpoints is unlimited theoretically.

SRAM

• 128 bytes internal direct access RAM

• 128 bytes internal indirect access RAM

• 8192 bytes internal extended RAM

Clock

• Internal high precise RC clock IRC(IRC for short, ranges from 4MHz to 45MHz), adjustable while ISP and can be divided to lower frequency by user software, 100KHz for instance.

– Error:±0.3%

– -1.38%～+1.42% temperature drift (at the temperature range of -40°C to +85°C)

– -0.88%～+1.05% temperature drift (at the temperature range of -20°C to 65°C)

• Internal 32KHz low speed IRC with large error

• External 4MHz~45MHz oscillator or external clock

Reset

• Hardware reset

– Power-on reset.

– Reset by reset pin. The default function of P5.4 is the I/O port. The P5.4 pin can be set as the reset pin while ISP download. (Note: When the P5.4 pin is set as the reset pin, the reset level is low.)

– Watch dog timer reset

– Low voltage detection reset. 4 low voltage detection levels are provided, 2.2V, 2.4V, V2.7,V3.0

• Software reset

– Writing the reset trigger register using software

Interrupts

• 43 interrupt sources: INT0(Supports rising edge and falling edge interrupt), INT1(Supports rising edge and falling edge interrupt), INT2(Supports falling edge interrupt only), INT3(Supports falling edge interrupt only), INT4(Supports falling edge interrupt only), timer 0, timer 1, timer 2, timer 3, timer 4, UART 1, UART 2, UART 3, UART 4, ADC, LVD, SPI, I2C, comparator, PWMA, PWMB, RTC, TKS, P1, P2, P3, P4, P5,P6,P7, LCD driver, DMA receive and transmit interrupts of UART 1, DMA receive and transmit interrupts of UART 2, DMA receive and transmit interrupts of UART 3, DMA receive and transmit interrupts of UART 4, DMA interrupt of SPI, DMA interrupt of ADC, DMA interrupt of LCD driver and DMA interrupt of memory-to-memory.

• 4 interrupt priority levels

• Interrupts that can wake up the CPU in clock stop mode: INT0(P3.2), INT1(P3.3), INT2(P3.6), INT3(P3.7), INT4(P3.0), T0(P3.4), T1(P3.5), T2(P1.2), T3(P0.4), T4(P0.6), RXD(P3.0/P3.6/P1.6/P4.3), RXD2(P1.0/P4.0), RXD3(P0.0/P5.0), RXD4(P0.2/P5.2),CCP0(P1.7/P2.3/P7.0/P3.3) ,CCP1(P1.6/P2.4/P7.1/P3.2) ,CCP2(P1.5/P2.5/P7.2/P3.1) , CCP3(P1.4/P2.6/P7.3/P3.0), I2C_SDA(P1.4/P2.4/P3.3), SPI_SS(P1.2/P2.2/P3.5), Comparator interrupt, LVD interrupt, Power-down wake-up timer and interrupts of all I/O ports.

Digital peripherals

• 5 16-bit timers: timer0, timer1, timer2, timer3, timer4. Where the mode 3 of timer0 has the Non Maskable Interrupt (NMI in short) function. Mode 0 of timer0 and timer1 is 16-bit Auto-reload mode.

• 4 high speed UARTs: uart1, uart2,uart3, uart4, whose baud rate clock source may be fast as FOSC/4

• 4 groups of PCA: CCP0, CCP1, CCP2, CCP3, which can be used as capture, high speed output and 6-bits, 7-bits, 8-bits or 10-bits PWM

• 8 groups of 15 bit enhanced PWM. Control signal with dead zone can be realized, and external fault detection function is supported.

• SPI: Master mode, slave mode or master/slave automatic switch mode are supported.

• I2C: Master mode or slave mode are supported.

• MDU16: Hardware 16-bit Multiplier and Divider which supports 32-bit divided by 16-bit, 16-bit divided by 16-bit, 16-bit multiplied by 16-bit, data shift, and data normalization operations.

• I/O port interrupt: All I/Os support interrupts, each group of I/O interrupts has an independent interrupt entry address, all I/O interrupts can support 4 types interrupt mode: high level interrupt, low level interrupt, rising edge interrupt, falling edge interrupt. Provides 4 levels of interrupt priority and supports power-down wake-up function.

• DMA: Support SPI shift to receive data to memory, SPI shift to send data from memory, I2C send data from memory, I2C receive data to memory, USART 1/2 and UART 3/4 receive data to memory, USART 1/2 and UART 3/4 send data from memory, ADC automatically sample data to memory (calculate average value at the same time), LCD driver send data from memory, and copy data from memory to memory

• LCD (TFT color screen) dirver: support 8080 and 6800 interface, and support 8-bit and 16-bit data width (Note: A version of the chip does not have this function)

• Hardware digital ID: support 32 bytes

Analog peripherals

• Ultra high speed ADC which supports 12-bit precision 15 channels (channel 0 to channel 14)maximum speed can be 800K(800K ADC conversions per second)

• ADC channel 15 is used to test the internal reference voltage. (The default internal reference voltage is 1.19V when the chip is shipped, the error is ±1%)

• Comparator. A set of comparator

• DAC: 8 channels advanced PWM timer can be used as 8 channels DAC

GPIO

• Up to 59 GPIOs: P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.4, P5.0~P5.5, P6.0~P6.7, P7.0~P7.7

• 4 modes for all GPIOs: quasi-bidirectional mode, push-pull output mode, open drain mode,high-impedance input mode

Package

• LQFP64, LQFP48, LQFP44