STC15W4K32S4 series

Features:

• Enhanced 8051 Central Processing Unit, 1T, single clock per machine cycle, faster 8~12 times than the rate of a traditional 8051.
• Operating voltage range : 5.5V ~ 2.5V.
• On-chip 16K/32K/40K/48K/56K/58K/61K/63.5K FLASH program memory with flexible ISP/IAP capability,can be repeatedly erased more than 100 thousand times.
• Large capacity of on-chip 4096 bytes SRAM: 256 byte scratch-pad RAM and 3840 bytes of auxiliary RAM
• Be capable of addressing up to 64K byte of external RAM
• On-chip EEPROM with large capacity can be repeatedly erased more than 100 thousand times.
• Dual Data Pointer (DPTR) to speed up data movement
• ISP/IAP, In-System-Programming and In-Application-Programming , no need for programmer and emulator.
• 8 channels and 10 bits Analog-to-Digital Converter (ADC), the speed up to 300 thousand times per second, 3 channels PWM also can be used as 3 channels D/A Converter(DAC).
• 6 channels 15 bits high-precision PWM (with a dead-section controller) and 2 channels CCP (The high-speed pulse function of which can be utilized to realize 11 ~ 16 bits PWM)
  ---- can be used as 8 channels D/A Converter or 2 Times or 2 external Interrupts (which can be generated on rising or falling edge).
• Internal hghly reliable Reset with 16 levels optional threshold voltage of reset,so that external reset curcuit can be completely removed.
• Internal high- precise R/C clock(±0.3%) with ±1% temperature drift (-40~+85°C) while ±0.6% (-20~+65°C) in normal temperature and wide frenquency adjustable between 5MHz and 35MHz (5.5296MHz /11.0592MHz / 22.1184MHz / 33.1776MHz).
• Operating frequency range: 5- 35MHz, is equivalent to traditional 8051:60~420MHz.
• Four high-speed asynchronous serial ports----UARTs (UART1/UART2/UART3/UART4 can be usedsimultaneously and regarded as 9 serial ports by shifting among 9 groups of pins):
  --UART1(RxD/P3.0, TxD/P3.1) can be switched to (RxD_2/P3.6, TxD_2/P3.7),also can be switched to (RxD_3/P1.6, TxD_3/P1.7);
  --UART2(RxD2/P1.0, TxD2/P1.1) can be switched to (RxD2_2/P4.6, TxD2_2/P4.7);
  --UART3(RxD3/P0.0, TxD3/P0.1) can be switched to (RxD3_2/P5.0, TxD3_2/P5.1);
  --UART4(RxD4/P0.2, TxD4/P0.3) can be switched to (RxD4_2/P5.2, TxD4_2/P5.3)
• A high-speed synchronous serial peripheral interface----SPI.
• Support the function of Encryption Download (to protect your code from being intercepted).
• Support the function of RS485 Control
• Code protection for flash memory access, excellent noise immunity, very low power consumption
• Power management mode: Slow-Down mode, Idle mode(all interrupt can wake up Idle mode),Stop/Power- Down mode.
• Timers which can wake up stop/power-down mode: have internal low-power special wake-up Timer.
• Resource which can wake up stop/power-down mode are:
  INT0/P3.2, INT1/P3.3 (INT0/INT1, may begenerated on both rising and falling edges), INT2/P3.6, INT3/P3.7, INT4/P3.0 (INT2 /INT3/INT4, only be generated on falling edge);pins CCP0/CCP1; pins RxD/RxD2/ RxD3/RxD4; pins T0/T1/T2/T3/T4(their falling edge can wake up if T0/T1/T2/T3/T4 have been enabled before power-down mode, but no interrupts can be generatetd); internal low-power special wake-up Timer.
• 7 Timers/Counters: five 16-bit reloadable Timers/Counters (T0/T1/T2/T3/T4, T0 and T1 are compatible with Timer0/Timer1 of traditional 8051) and 2 Timers which maybe realized by 2 channels CCP.T0/T1/T2/T3/T4 all can independently achieve external programmable clock output (5 channels) .
• Programmable clock output function(output by dividing the frequency of the internal system clock or the input clock of external pin):
  ①The Programmable clock output of T0 is on P3.5/T0CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T0/P3.4)
  ②The Programmable clock output of T1 is on P3.4/T1CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T1/P3.5)
  ③The Programmable clock output of T2 is on P3.0/T2CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T2/P3.1)
  ④The Programmable clock output of T3 is on P0.4/T3CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T3/P0.5)
  ⑤he Programmable clock output of T4 is on P0.6/T4CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T4/P0.7)
  Five timers/counters in above all can be output by dividing the frequency from 1 to 65536.
  ⑥The Programmable clock output of master clock is on P5.4/MCLKO, and its frequency can be divided into MCLK/1, MCLK/2, MCLK/4, MCLK/16.
  The master clock can either be internal R/C clock or the external input clock or the external crystal oscillator.
  MCLK is the frequency of master clock. MCLKO is the output of master clock.
• Comparator, which can be used as 1 channel ADC or brownout detect function and support comparing by external pin CMP+ and CMP- or internal reference voltage and generating output signal (its polarity can be configured) on CMPO pin.
• One 15 bitsWatch-Dog-Timer with 8-bit pre-scaler (one-time-enabled)
• advanced instruction set, which is fully compatible with traditional 8051 MCU, have hardware multiplication / division command.
• 62/46/42/38/30/26 common I/O ports are available, their mode is quasi_bidirectional/weak pull-up(traditional 8051 I/O ports mode) after reset, and can be set to four modes: quasi_bidirectional /weak pull-up, strong pushpull/ strong pull-up, input-only/high-impedance and open drain.
• the driving ability of each I/O port can be up to 20mA, but it don't exceed this maximum 120mA that the current of the whole chip of 40-pin or more than 40-pin MCU, while 90mA that the current of the whole chip of 16-pin or more than 16-pin MCU or 32-pin or less than 32-pin MCU.
• Package: LQFP64L, LQFP64S, LQFP48, LQFP44, LQFP32, SOP28, SKDIP28, PDIP40.
• All products are baked 8 hours in high-temperature 175°C after be packaged ,Manufacture guarantee good quality.
• In Keil C development environment, select the Intel 8052 to compiling and only contain < reg51.h >