STC8H1K08 series

Features:

Core

• Ultra-high speed 8051 Core with single clock per machine cycle, which is called 1T, and the speed is about 12 times faster than traditional 8051

• Fully compatible instruction set with traditional 8051

• 17interrupt sources and 4 interrupt priority levels

• Online debugging is supported

Operating voltage

• 1.9 to 5.5V

Operating temperature

• -40°C~85°C

Flash memory

• Up to 17Kbytes of Flash memory to be used for storing user code

• Configurable size EEPROM, 512bytes single page for being erased, which can be repeatedly erased more than 100 thousand times.

• In-System-Programming, ISP in short, can be used to update the application code. No dedicated programmer is needed.

• Online debugging with single chip is supported, and no dedicated emulator is needed. The number of breakpoints is unlimited theoratically.

SRAM

• 128 bytes internal direct access RAM (DATA, use keyword data to declare in C language program)

• 128 bytes internal indirect access RAM (IDATA, use keyword idata to declare in C language program)

• 1024 bytes internal extended RAM (internal XDATA, use keyword xdata to declare in C language program)

Clock

• Internal high precise RC clock(IRC for short, ranges from 4MHz to 36MHz), adjustable while ISP and can be divided to lower frequency by user software, 100KHz for instance.

– Error:±0.3%

– -1.35%～+1.30% temperature drift (at the temperature range of -40℃ to +85℃)

– -0.76%～+0.98% temperature drift (at the temperature range of -20℃ to 65℃)

• Internal 32KHz low speed IRC with large error

• External 4MHz~33MHz oscillator or external clock

• The three clock source above can be selected freely by used code.

Reset

• Hardware reset

– Power-on reset

– Reset by reset pin. The default function of P5.4 is the I/O port. P5.4 pin can be set as the reset pin while ISP download.

– Watch dog timer reset

– Low voltage detection reset. 4 low voltage detection levels are provided, 2.0V, 2.4V, V2.7,V3.0

• Software reset

– Writing the reset trigger register using software

Interrupts

• 17 interrupt sources: INT0(Supports rising edge and falling edge interrupt), INT1(Supports rising edge and falling edge interrupt), INT2(Supports falling edge interrupt only), INT3(Supports falling edge interrupt only), INT4(Supports falling edge interrupt only), timer 0, timer 1, timer 2, UART 1, UART 2, ADC, LVD, SPI, I2C, comparator, PWMA, PWMB

• 4 interrupt priority levels

• Interrupts that can wake up the CPU in clock stop mode: INT0(P3.2), INT1(P3.3), INT2(P3.6), INT3(P3.7), INT4(P3.0), T0(P3.4), T1(P3.5),T2(P1.2), RXD(P3.0/P3.6/P1.6), RXD2(P1.0), I2C_SDA(P1.4/P3.3), Comparator interrupt, LVD interrupt,Power-down wake-up timer.

Digital peripherals

• 3 16-bit timers: timer0, timer1, timer2, where the mode 3 of timer 0 has the Non-Maskable Interrupt (NMI in short) function. Mode 0 of timer 0 and timer 1 is 16-bit Auto-reload mode.

• 2 high speed UARTs: UART1, UART2, whose maximum baudrate clock may be FOSC/4

• 8 channels/2 groups of enhanced PWMs, which can realize control signals with dead time, and support external fault detection function. In addition,it also supports 16-bit timers, 8 external interrupts, 8 channels of external capture and pulse width measurement functions.

• SPI: Master mode, slave mode or master/slave automatic switch mode are supported.

• I2C: Master mode or slave mode are supported.

Analog peripherals

• 9 channels (channel 0 to channel 1, channel 8 to channel 14) ultra high speed ADC which supports 10-bit precision. The maximum speed can be 500K(Half a million ADC conversions per second)

• Channel 15 of ADC is used to test the internal reference voltage.

• A set of comparator

• DAC: 8 channels advanced PWMs timers can be used as 8 channels DAC

GPIO

• Up to 17 GPIOs: P1.0~P1.7, P3.0~P3.7, P5.4

• 4 modes for all GPIOs: quasi-bidirectional mode, push-pull output mode, open drain mode, high-impedance input mode

• Except for P3.0 and P3.1, all other I/O ports are in a high-impedance state after power-on. User must configure the I/O ports mode before using them. In addition, the internal 4K pull-up resistor of every I/O can be enabled independently.

Package

• TSSOP20，QFN20