STC8G2K64S2 series

Features:

Core

• Enhanced 8051 Core with single clock per machine cycle (1T)

• Fully compatible instruction set with traditional 8051

• 27 interrupt sources and 4 interrupt priority levels

• Online debugging is supported

Operating voltage

• 1.9 to 5.5V

• Built-in LDO

Operating temperature

• -40°C~85°C

Flash memory

• Up to 64Kbytes of Flash memory to be used to store user code

• Configurable EEPROM size, 512bytes single page erased, can be repeatedly erased more than 100 thousand times.

• In-System-Programming, ISP in short, can be used to update the application code, no need for programmer.

• Online debugging with single chip is supported, and no emulator is needed. The number of breakpoints is unlimited theoretically.

SRAM

• 128 bytes internal direct access RAM

• 128 bytes internal indirect access RAM

• 2048 bytes internal extended RAM

Clock

• Internal high precise R/C clock (IRC, range from 4MHz to 36MHz), adjustable while ISP and can be divided to lower frequency by user software, 100KHz for instance.

– Error:±0.3%

– -1.38%～+1.42% temperature drift (at the temperature range of -40℃ to +85℃)

– -0.88%～+1.05% temperature drift (at the temperature range of -20℃ to 65℃)

• Internal 32KHz low speed IRC with large error

• External 4MHz~33MHz oscillator or external clock

• The three clock source above can be selected freely by used code.

Reset

• Hardware reset

– Power-on reset. Measured voltage value is 1.69V~1.82V. (Effective when the chip does not enable the low voltage reset function)

– Reset by reset pin. The default function of P5.4 is the I/O port. The P5.4 pin can be set as the reset pin while ISP download

– Watch dog timer reset

– Low voltage detection reset. 4 low voltage detection levels are provided, 2.2V (Measured as 1.90V~2.04V), 2.4V (Measured as 2.30V~2.50V), V2.7 (Measured as 2.61V~2.82V), V3.0 (Measured as 2.90V~3.13V).

• Software reset

– Writing the reset trigger register using software

Interrupts

• 27 interrupt sources: INT0(Supports rising edge and falling edge interrupt), INT1(Supports rising edge and falling edge interrupt), INT2(Supports falling edge interrupt only), INT3(Supports falling edge interrupt only), INT4(Supports falling edge interrupt only), timer0, timer1, timer2, timer3, timer4, UART1, UART2, ADC, LVD, SPI, I2C, comparator, PCA/CCP/PWM, enhanced PWM2, enhanced PWM2 fault detection.

• 4 interrupt priority levels

• Interrupts that can awaken the CPU in clock stop mode: INT0 (P3.2), INT1 (P3.3), INT2 (P3.6), INT3 (P3.7), INT4 (P3.0), T0 (P3.4), T1(P3.5), T2(P1.2), T3(P0.4), T4(P0.6), RXD(P3.0/P3.6/P1.6/P4.3), RXD2(P1.4/P4.6), CCP0(P1.1/P3.5/P2.5), CCP1(P1.0/P3.6/P2.6), CCP2 (P3.7/P2.7), I2C_SDA (P1.4/P2.4/P3.3) and comparator interrupt, low-voltage detection interrupt, power-down wake-up timer.

Digital peripherals

• 5 16-bit timers: timer0, timer1, timer2. Where the mode 3 of timer0 has the Non Maskable Interrupt (NMI in short) function. Mode 0 of timer0 and timer1 is 16-bit Auto-reload mode.

• 2 high speed UARTs: uart1, uart2, whose baud rate clock source may be fast as FOSC/4

• 3 groups of 16-bit PCAs: CCP0, CCP1, CCP2, which can be used as capture, high speed output and 6-bits, 7-bits, 8-bits or 10-bits PWM.

• 8 groups of 15-bit enhanced PWMs, which can realize control signals with dead-time, and support external fault detection function. In addition, there are 3 groups of traditional PCA / CCP / PWM can be used as PWM.

• SPI: Master mode, slave mode or master/slave automatic switch mode are supported.

• I2C: Master mode or slave mode are supported.

• MDU16: Hardware 16-bit Multiplier and Divider which supports 32-bit divided by 16-bit, 16-bit divided by 16-bit, 16-bit by 16-bit, data shift, and data normalization operations.

Analog peripherals

• 15 channels (channel 0 to channel 14) ultra-high speed ADC which supports 10-bit precision analog-to-digital conversion.

• ADC channel 15 is used to test the internal reference voltage. (The default internal reference voltage is 1.19V when the chip is shipped)

• Comparator. A set of comparators (the positive terminal of the comparator can select the CMP+ and all ADC input ports, so the comparator can be used as a multi-channel comparator for time division multiplexing).

• DAC. 3 groups of PCAs can be used as DACs. 8 channels enhanced PWMs can be used as DACs

GPIO

• Up to 45GPIOs: P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.7, P5.0~P5.4,

• 4 modes for all GPIOs: quasi-bidirectional mode, push-pull output mode, open drain mode, high-impedance input mode

Package

• LQFP48，QFN48