STC32G8K64 series

Features:

Core

• Ultra-high speed 32-bit 8051 Core with single clock per machine cycle, which is called 1T and the speed is about 70 times faster than traditional 8051

• 48 interrupt sources and 4 interrupt priority levels

• Online debugging is supported

Operating voltage

• 1.9V~5.5V

• Built-in LDO

Operating temperature

• -40℃ ~ + 85℃

Flash memory

• Up to 64Kbytes of Flash memory to be used for storing user code

• Configurable EEPROM size, 512bytes single page for being erased, which can be repeatedly erased more than 100 thousand times.

• In-System-Programming, ISP in short, can be used to update the application code. No special programmer is needed.

• Online debugging with single chip is supported, and no special emulator is needed. The number of breakpoints is unlimited theoratically.

• Support hardware emulation of SWD interface (requires STC-USB Link1 tool)

SRAM

• 2K bytes internal SRAM (EDATA)

• 6K bytes internal extended RAM (internal XDATA

• Notes on using xdata:

• When defining variables, single-byte variables can be defined in xdata, and multi-byte (2-byte, 4-byte) variables need to be defined in edata.

Clock

• Internal high precise RC clock IRC(IRC， range from 4MHz to 38MHz), adjustable while ISP and can be divided to lower frequency by user software.

• Error:±0.3% (at the temperature 25℃)

• -1.35%～+1.30% temperature drift (at the temperature range of -40℃ to +85℃)

• -0.76%～+0.98% temperature drift (at the temperature range of -20℃ to 65℃)

• Internal 32KHz low speed IRC with large error

• External crystal (4MHz～33MHz) and external clock

• Internal PLL output clock

• Users can freely choose the above 4 clock sources

Reset

• Hardware reset

• Power-on reset. Measured voltage is 1.7V~1.9V. (Effective when the chip does not enable the low voltage reset function)

• Reset by reset pin. The default function of P5.4 is the I/O port. The P5.4 pin can be set as the reset pin while ISP download. (Note: When the P5.4 pin is set as the reset pin, the reset level is low.)

• Watch dog timer reset

• Low voltage detection reset. 4 low voltage detection levels are provided, 2.0V, 2.3V, 2.7V, 3.0V.

• Software reset

• Writing the reset trigger register using software

Interrupts

• 49 interrupt sources: INT0, INT1, INT2, INT3, INT4, timer 0, timer 1, timer 2, timer 3, timer 4, USART1, USART2, UART 3, UART 4, ADC, LVD, SPI, I2C, comparator, PWMA, PWMB, CAN, CAN2, LIN, LCMIF color screen interface, RTC, all I/O interrupts (8 groups), DMA receive and transmit interrupts of USART 1, DMA receive and transmit interrupts of USART 2, DMA receive and transmit interrupts of UART 3, DMA receive and transmit interrupts of UART 4, DMA interrupt of I2C, DMA interrupt of SPI, DMA interrupt of ADC, DMA interrupt of LCD driver and DMA interrupt of memory-to-memory.

• 4 interrupt priority levels

Digital peripherals

• 5 16-bit timers: timer0, timer1, timer2, timer3, timer4, where the mode 3 of timer 0 has the Non-Maskable Interrupt (NMI in short) function. Mode 0 of timer 0 and timer 1 is 16-bit Auto-reload mode.

• 2 high speed USARTs: USART1, USART2, whose maximum baudrate clock may be FOSC/4. The following modes are supported, synchronous serial port mode, asynchronous serial port mode, SPI mode, LIN mode, infrared mode (IrDA), smart card mode (ISO7816)

• 2 high speed UARTs: UART3, UART4, whose maximum baudrate clock may be FOSC/4

• 2 groups of enhanced PWM, which can realize 8 channels(4 groups complementary symmetry) control signals with dead time, and support external fault detection function.

• SPI: Master mode, slave mode or master/slave automatic switch mode are supported.

• I2C: Master mode or slave mode are supported.

• ICE: Hardware support emulation.

• RTC: Support year, month, day, hour, minute, second, sub-second (1/128 second). And supports clock interrupt and a set of alarm clocks.

• CAN: Two independent CAN 2.0 control units.

• LIN: An independent LIN control unit (supports versions 1.3 and 2.1), USART1 and USART2 can support two sets of LIN.

• MDU32: Hardware 32-bit Multiplier and Divider which supports 32-bit divided by 32-bit, 32-bit multiplied by 32-bit operations.

• I/O port interrupt: All I/Os support interrupts, each group of I/O interrupts has an independent interrupt entry address, all I/O interrupts can support 4 types interrupt mode: high level interrupt, low level interrupt, rising edge interrupt, falling edge interrupt. Provides 4 levels of interrupt priority and supports power-down wake-up function.

• LCD dirver: support 8080 and 6800 interface, and support 8-bit and 16-bit data width.

• DMA: Support SPI shift to receive data to memory, SPI shift to send data from memory, I2C send data from memory, I2C receive data to memory, USART 1/2 and UART 3/4 receive data to memory, USART 1/2 and UART 3/4 send data from memory, ADC automatically sample data to memory (calculate average value at the same time), LCD driver send data from memory, and copy data from memory to memory

• Hardware digital ID: support 32 bytes

Analog peripherals

• Ultra high speed ADC which supports 12-bit precision 15 channels (channel 0 to channel 14) analog-to-digital conversion. ADC channel 15 is used to test the internal reference voltage. (The default internal reference voltage is 1.19V when the chip is shipped, the error is ±1%)

• Comparator. A set of comparator

GPIO

• Up to 45 GPIOs: P0.0~P0.7, P1.0~P1.7(No P1.2), P2.0~P2.7, P3.0~P3.7, P4.0~P4.7, P5.0~P5.4.

• 4 modes for all GPIOs: quasi_bidirectional mode, push-pull outputmode, open drain mode, high-impedance input mode

• Except for P3.0 and P3.1, all other I/O ports are in a high-impedance state after power-on. User must set the I/O ports mode before using them. In addition, the internal 4K pull-up resistor of every I/O can be enabled independently.

Package

• LQFP48、QFN48、LQFP32、QFN32、TSSOP20