STC32G144K246 series

Features:

Core & Performance

• Ultra-high speed 32-bit 8051 Core with single clock per machine cycle (1T), about 70 times faster than traditional 8051.

• 100MHz~120MHz CPU/DSP, supporting 240MHz TFPU / PWM.

• Over 49 interrupt sources, 4 interrupt priority levels.

• Supports USB and SWD online debugging.

Operating Voltage & Temperature

• Operating voltage: 1.9V ~ 5.5V (requires ≥3.0V when temperature is below -40℃).

• Built-in LDO.

• -20℃ ~ +65℃ (internal high-speed IRC temp drift -0.76% ~ +0.98%).

• -40℃ ~ +85℃ (internal high-speed IRC temp drift ±1.3%).

• -40℃ ~ +125℃ (requires external crystal / internal PLL when above 85℃).

Flash Memory

• Up to 246 Kbytes of Flash program memory (ROM) used for storing user code.

• Supports user-configurable part of Flash used as DATA FLASH/EEPROM, 512 bytes single page erased, typical endurance over 100,000 cycles.

• Supports hardware USB direct download and standard UART ISP download.

• Supports hardware SWD real-time emulation via P3.0/P3.1 (requires STC-USB Link1 tool).

• Flash data retention: over 100 years (@25℃), over 20 years (@105℃).

SRAM (Total 144K + 4K bytes)

• 16K bytes internal SRAM (edata).

• 128K bytes internal extended RAM (internal xdata).

• 4K bytes high-end extended RAM (can be mapped to 80H:0000H~80H:0FFFH region to execute user programs).

Clock Control

• Internal high-precision high-speed IRC (adjustable during ISP programming):

– Error ±0.3% (at 25℃ room temperature)

– -1.35% ~ +1.30% temp drift (full temp range -40℃ ~ 85℃)

– -0.76% ~ +0.98% temp drift (temp range -20℃ ~ 65℃)

• Internal 32KHz low speed IRC (low power consumption, large error).

• External crystal (4MHz~40MHz) and external clock, built-in external clock anti-interference circuit, can use internal PLL to multiply to high frequency.

• Internal dual independent 500MHz PLLs, outputting 240MHz clock for TFPU, PWM, I2S, SPI, and other high-speed peripherals.

• Users can freely select from the above 4 clock sources.

Reset Mechanism

• Hardware reset:

– Power-on reset, reset voltage level is 1.7V ~ 1.9V (effective when LVD reset is not enabled)

– Reset pin reset (P5.4 pin can be configured as low-level reset pin)

– Watchdog timer overflow reset

– Low voltage detection reset, providing 4 detection levels: 2.0V, 2.4V, 2.7V, 3.0V

• Software reset: Writing to reset trigger register via software.

Digital Peripherals

• 14 16-bit timers: T0~T11, T17, T18 (Timer 0 Mode 3 supports NMI; T17/T18 can synchronously trigger two groups of ADC/DAC).

• 8 high-speed synchronous/asynchronous serial ports: USART1~USART8 (supports Synchronous, Asynchronous, SPI, LIN, IrDA, ISO7816 Smart Card modes).

• 24-channel advanced PWM: 3+3 groups of advanced PWM (PWMA/PWMC/PWME support 4 complementary pairs with dead-time control), PWM clock up to 240MHz.

• SPI: 3 independent hardware SPIs + 8 USART SPI modes, supporting 240MHz clock and DMA transfer.

• QSPI: Supports Single, Dual, and Quad wire modes.

• I2C: Two independent hardware I2Cs, supporting Master and Slave modes.

• RTC: Supports year, month, day, day-of-week, hour, minute, second, sub-second (1/128 sec), count values remain intact upon reset.

• USB: USB2.0/USB1.1 full-speed, 16 bidirectional endpoints with 64/128/256/512/1024-byte FIFO buffers.

• CAN: Two independent CAN-FD 2.0 control units.

• LIN: 2+8 hardware LINs (2 independent LINs + 8 USART LIN modes).

• I2S: Two independent I2S audio buses, supporting full-duplex recording and playback.

• DSP32 & TFPU: Hardware 32/64-bit DSP instructions (up to 74MHz) + Single-precision Floating Point Unit TFPU (up to 240MHz, supports basic arithmetic & trigonometric functions).

Analog Peripherals

• ADC: Dual independent ultra-high-speed ADCs, supporting 12-bit high-precision 15 channels (Ch 0~14), Channel 15 tests internal reference voltage (1.19V ±1%).

• DAC: Dual independent 12-bit high-speed DACs, output can directly connect to internal Comparators and OPAs.

• Comparator: 4 independent 6P6N mode comparators (CMP).

• Operational Amplifier: 4 independent operational amplifiers (OPA).

GPIO & Bus Interfaces

• Up to 91 GPIOs: P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.7, P5.0~P5.4, P6.0~P6.7, P7.0~P7.7, P8.0~P8.7, P9.0~P9.7, PA.0~PA.7, PB.0~PB.7.

• Supports 4 modes: Quasi-bidirectional, Push-pull output, Open-drain, High-impedance input (High-impedance input by default upon power-on).

• Each I/O pin supports independent internal pull-up and pull-down resistors.

• All I/O pins support 4 interrupt modes and power-down wake-up.

• LCD/TFT Color Screen Driver Interface: Supports 8080 and 6800 interfaces (8-bit/16-bit data width, supports big/little-endian).

Package

• LQFP100, LQFP64, LQFP48, LQFP44.