STC15W404S series

Features:

• Enhanced 8051 Central Processing Unit, 1T, single clock per machine cycle, faster 8~12 times than the rate of a traditional 8051.
• Operating voltage range: 5.5V ~ 2.5V.
• On-chip 4K / 8K / 10K / 13K / 15.5K FLASH program memory with flexible ISP/IAP capability, can be repeatedly erased more than 100 thousand times.
• on-chip 512 bytes SRAM: 256 byte scratch-pad RAM and 256 bytes of auxiliary RAM
• Be capable of addressing up to 64K byte of external RAM
• On-chip EEPROM with large capacity can be repeatedly erased more than 100 thousand times.
• Dual Data Pointer (DPTR) to speed up data movement
• ISP/IAP, In-System-Programming and In-Application-Programming , no need for programmer and emulator.
• Internal hghly reliable Reset with 16 levels optional threshold voltage of reset, external reset curcuit can be completely removed
• Internal high- precise R/C clock(±0.3%) with ±1% temperature drift (-40°C to +85°C)) while 0.6%(-20℃ to 65℃)) in normal temperature and wide frenquency adjustable between 5MHz and 35MHz (5.5296MHz / 11.0592MHz / 22.1184MHz / 33.1776MHz)
• No need external crystal and reset, and can output clock and low reset signal from MCU.
• Operating frequency range: 5- 35MHz, is equivalent to traditional 8051 : 60 ~ 420MHz.
• A high-speed asynchronous serial port----UART( can be used simultaneously and regarded as 3 serial ports by shifting among 3 groups of pins):
  UART1(RxD/P3.0, TxD/P3.1) can be switched to (RxD_2/P3.6, TxD_2/P3.7),also can be switched to(RxD_3/P1.6, TxD_3/P1.7).
• A high-speed synchronous serial peripheral interface----SPI.
• Support the function of Encryption Download (to protect your code from being intercepted).
• Support the function of RS485 Control
• Code protection for flash memory access, excellent noise immunity, very low power consumption
• Power management mode: Slow-Down mode, Idle mode(all interrupt can wake up Idle mode), Stop/Power- Down mode.
• Timers which can wake up stop/power-down mode: have internal low-power special wake-up Timer.
• Resource which can wake up stop/power-down mode are:
  INT0/P3.2, INT1/P3.3 (INT0/INT1, may begenerated on both rising and falling edges),INT2/P3.6, INT3/P3.7, INT4/P3.0 ( INT2/ INT3/ INT4, only be generated on fallingedge);pins RxD; pins T0/T1/T2(their fallingedge can wake up if T0/T1/T2 have been enabled before power-down mode, but no interrupts can be generatetd); internal low- power special wake-up Timer.
• threee 16-bit reloadable Timers/Counters(T0/T1/T2, T0 and T1 are compatible with Timer0/Timer1 of traditional 8051), T0/T1/T2 all can independently achieve external programmable clock output (3 channels).
• Programmable clock output function(output by dividing the frequency of the internal system clock or the input clock of external pin):
  The speed of external programmable clock output of 5V MCU is also not more than 13.5MHz,because the output speed of I/O port of STC15 series 5V MCU is not more than 13.5MHz.
  The speed of external programmable clock output of 3.3V MCU is also not more than 8MHz,because the output speed of I/O port of STC15 series 3.3V MCU is not more than 8MHz.
  ①The Programmable clock output of T0 is on P3.5/T0CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T0/P3.4)
  ② The Programmable clock output of T1 is on P3.4/T1CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T1/P3.5)
  ③ The Programmable clock output of T2 is on P3.0/T2CLKO (output by dividing the frequency of the internal system clock or the input clock of external pin T2/P3.1)
  Three timers/counters in above all can be output by dividing the frequency from 1 to 65536.
  ④ The Programmable clock output of master clock is on P5.4/MCLKO or P1.6/XTAL2/MCLKO_2, and its frequency can be divided into MCLK/1, MCLK/2, MCLK/4.
  The master clock can either be internal R/C clock or the external input clock or the external crystal oscillator.
  MCLK is the frequency of master clock. MCLKO is the output of master clock.
  It is on MCLKO/P3.4 that the Programmable clock output of master clock of STC15 series 8-pin MCU (such as STC15F101W series). However, it is on MCLKO/P5.4 that the Programmable clock output of master clock of other STC15 series MCU including 16-pin or more than 16-pin MCU(such as STC15F2K60S2, STC15W4K32S4 and so on)
• Comparator, which support comparing by external pin CMP+ and CMP- or internal reference voltage and generating output signal(its polarity can be configured) on CMPO pin can be used as 1 channel ADC or brownout detect function.
• One 15 bits Watch-Dog-Timer with 8-bit pre-scaler (one-time-enabled)
• advanced instruction set, which is fully compatible with traditional 8051 MCU, have hardware multiplication / division command.
• 42/38/30/26 common I/O ports are available, their mode is quasi_bidirectional/weak pull-up (traditional 8051 I/O ports mode) after reset, and can be set to four modes:quasi_bidirectional/weak pull-up, strong push-pull/ strong pull-up, input-only/high-impedance and open drain.
• the driving ability of each I/O port can be up to 20mA, but it dont exceed this maximum 120mA that the current of the whole chip of 40-pin or more than 40-pin MCU, while 90mA that the current of the whole chip of 16-pin or more than 16-pin MCU or 32-pin or less than 32-pin MCU.
• If I/O ports are not enough, it can be extended by connecting a 74HC595. Besides,cascading several chips also can extend to dozens of I/O ports.
• Package: LQFP44 (12mm x 12mm), LQFP32 (9mm x 9mm), SOP28, SKDIP28, PDIP40.
• All products are baked 8 hours in high-temperature 175°C after be packaged, Manufacture guarantee good quality.
• In Keil C development environment, select the Intel 8052 to compiling and only contain < reg51.h >as header file