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Product>>8051 MicroController>>STC8A8K64S4A12 series


Features:

 

Core
• Enhanced 8051 Core with single clock per machine cycle (1T)
• Fully compatible instruction set with traditional 8051
• 22 interrupt sources and 4 interrupt priority levels
• Online debugging is supported
Operating voltage
• 2.0 to 5.5V
• Built-in LDO
Operating temperature
• -40°C~85°C
Flash memory
• Up to 64Kbytes of Flash memory to be used to store user code
• Configurable EEPROM size, 512bytes single page erased, can be repeatedly erased more than 100 thousand times.
• In-System-Programming, ISP in short, can be used to update the application code, no need for programmer.
• Online debugging with single chip is supported, and no emulator is needed. The number of breakpoints is unlimited theoretically.
SRAM
• 128 bytes internal direct access RAM
• 128 bytes internal indirect access RAM
• 8192 bytes internal extended RAM
• RAM expandable externally up to 64 Kbytes
Clock
• Internal 24MHz high precise R/C clock IRC
– Error:±0.3%
– Temperature drift: ±1.0% at the temperature range of -40°C to 85°C and ±0.6% at the temperature range of -20°C to 65°C
• Internal 32KHz low speed IRC with large error
• External 4MHz~33MHz oscillator or external clock
• The three clock source above can be selected freely by used code.
Reset
• Hardware reset
– Power-on reset
– Reset by reset pin with high reset pulse
– Watch dog timer reset
– Low voltage detection reset. 4 low voltage detection levels are provided, 2.2V, 2.4V, V2.7,V3.0
• Software reset
– Writing the reset trigger register using software
Interrupts
• 22 interrupt sources: INT0, INT1, INT2, INT3, INT4, timer0, timer1, timer2, timer3, timer4, uart1, uart2, uart3, uart4, ADC, LVD, PCA/CCP, SPI, I2C, comparator, enhanced PWM, enhanced PWM fault detection
• 4 interrupt priority levels
Digital peripherals
• 5 16-bit timers: timer0, timer1, timer2, timer3, timer4. Where the mode 3 of timer0 has the Non Maskable Interrupt (NMI in short) function. Mode 0 of timer0 and timer1 is 16-bit Auto-reload mode.
• 4 high speed UARTs: uart1, uart2,uart3, uart4, whose baud rate clock source may be fast as FOSC/4
• 4 groups of PCA: CCP0, CCP1, CCP2, CCP3, which can be used as capture, high speed output and 6-bits, 7-bits, 8-bits or 10-bits PWM
• 8 groups of 15 bit enhanced PWM. Control signal with dead zone can be realized, and external fault detection function is supported.
• SPI: Master mode, slave mode or master/slave automatic switch mode are supported.
• I2C: Master mode or slave mode are supported.
Analog peripherals
• ADC: 16 channels 10 bit ADC
• Comparator
GPIO
• Up to 62 GPIOs: P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.7, P5.0~P5.5, P6.0~P6.7, P7.0~P7.7
• 4 modes for all GPIOs: quasi-bidirectional mode, push-pull output mode, open drain mode,high-impedance input mode
Package
• LQFP64, LQFP48, LQFP44

 

Product Documents:

General Overview: STC8A8K64S4A12_Features.pdf

Data Sheet: STC8A8K64S4A12.pdf

ROSH£º

Product Support:

ISP programming software £ºSTC ISP programming software (v6.86)

Sample & Buy£º

Sample£ºSample Request Form

Buy £ºBuy Online

 

STC8A8K64S4A12 series Selection Table£º

 

Type
1T 8051
MCU
Oper
ating
Voltage
(V)
Flash
(byte)
S
R
A
M
(by
-te)
U
A
R
T
S
P
I

I
I
C
T
I
M
E
R
8 channels
PWM
SpeIcal
Power
-down
Wake-
up
Timer
Stan
-dard
Exter
-nal
Inter
rupts
A/D
15-
ch
C
O
M
P
A
R
A
T
O
R
D
P
T
R
EEP ROM Inter
-nal
Low-
Voltage
Detec
-tion
Inter
-rupt
W
D
T
Internal
High-
reliable
Reset
(with
optional
threshold
voltage)
Inter
-nal
High-
Pre
cise
Clock
Output
clock
and reset
signal
from
MCU
Encry
-pti on
Downl
oad(to
protect
your
code
from
being
interc
epted)
R
S
4
8
5
C
o
n
t
r
o
l
15-bit special
PWM
(with a
dead-
section
control
er)
10-bit CCP
PCA
PWM
STC8A8K64S4A12 series MCU Selection and Price Table
Note:
STC8A8K16S4A12 2.0-5.5 16K 8K 4 Y 5 8-ch 4-ch Y 5 12b Y 2 48K Y Y 4-level Y Y Y Y
STC8A8K32S4A12 2.0-5.5 32K 8K 4 Y 5 8-ch 4-ch Y 5 12b Y 2 32K Y Y 4-level Y Y Y Y
STC8A8K60S4A12 2.0-5.5 60K 8K 4 Y 5 8-ch 4-ch Y 5 12b Y 2 4K Y Y 4-level Y Y Y Y
STC8A8K64S4A12 2.0-5.5 64K 8K 4 Y 5 8-ch 4-ch Y 5 12b Y 2 IAP Y Y 4-level Y Y Y Y