Enhanced 8051 Central Processing Unit, 1T, single clock per machine cycle, faster 8~12 times
than the rate of
a traditional 8051.
capability,can be repeatedly erased more than 100 thousand times.
per second, 3
channels PWM also can be used as 3 channels D/A Converter(DAC).
(The high-speed pulse function of which can be utilized to realize 11 ~ 16 bits PWM)
---- can be used as 8 channels D/A Converter or 2 Times or 2 external Interrupts
(which can be generated on
rising or falling edge).
so that external reset curcuit
can be completely removed.
in normal temperature and wide frenquency adjustable between 5MHz and 35MHz (5.5296MHz /
11.0592MHz / 22.1184MHz / 33.1776MHz).
--UART1(RxD/P3.0, TxD/P3.1) can be switched to (RxD_2/P3.6, TxD_2/P3.7),
also can be switched to (RxD_3/P1.6, TxD_3/P1.7);
--UART2(RxD2/P1.0, TxD2/P1.1) can be switched to (RxD2_2/P4.6, TxD2_2/P4.7);
--UART3(RxD3/P0.0, TxD3/P0.1) can be switched to (RxD3_2/P5.0, TxD3_2/P5.1);
--UART4(RxD4/P0.2, TxD4/P0.3) can be switched to (RxD4_2/P5.2, TxD4_2/P5.3)
Stop/Power- Down mode.
Timers which can wake up stop/power-down mode: have internal low-power special wake-up Timer.
INT0/P3.2, INT1/P3.3 (INT0/INT1, may begenerated on both rising and falling edges),
INT2/P3.6, INT3/P3.7, INT4/P3.0 (INT2 /INT3/INT4, only be generated on falling edge);
pins CCP0/CCP1; pins RxD/RxD2/ RxD3/RxD4; pins T0/T1/T2/T3/T4(their falling edge can wake up
if T0/T1/T2/T3/T4 have been enabled before power-down mode, but no interrupts can be generatetd);
low-power special wake-up Timer.
with Timer0/Timer1 of traditional 8051) and 2 Timers which maybe realized by 2 channels CCP.
all can independently achieve external programmable clock output (5 channels) .
or the input clock of external pin):
The Programmable clock output of T0 is on P3.5/T0CLKO (output by dividing the frequency of the
internal system clock or the input clock of external pin T0/P3.4)
The Programmable clock output of T1 is on P3.4/T1CLKO (output by dividing the frequency of the
internal system clock or the input clock of external pin T1/P3.5)
The Programmable clock output of T2 is on P3.0/T2CLKO (output by dividing the frequency of the
internal system clock or the input clock of external pin T2/P3.1)
The Programmable clock output of T3 is on P0.4/T3CLKO (output by dividing the frequency of the
internal system clock or the input clock of external pin T3/P0.5)
The Programmable clock output of T4 is on P0.6/T4CLKO (output by dividing the frequency of the
internal system clock or the input clock of external pin T4/P0.7)
Five timers/counters in above all can be output by dividing the frequency from 1 to 65536.
The Programmable clock output of master clock is on P5.4/MCLKO, and its frequency can be divided
into MCLK/1, MCLK/2, MCLK/4, MCLK/16.
The master clock can either be internal R/C clock or the external input clock or the external crystal
MCLK is the frequency of master clock. MCLKO is the output of master clock.
by external pin CMP+ and CMP- or internal reference voltage and generating output signal (its polarity
configured) on CMPO pin.
(traditional 8051 I/O ports mode) after reset, and can be set to four modes: quasi_bidirectional /weak
pull-up, strong pushpull/ strong pull-up, input-only/high-impedance and open drain.
the driving ability of each I/O port can be up to 20mA, but it don't exceed this maximum 120mA that
the current of the whole chip of 40-pin or more than 40-pin MCU, while 90mA that the current of the
of 16-pin or more than 16-pin MCU or 32-pin or less than 32-pin MCU.
Data Sheet: STC15W4K32S4.pdf
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